1. Technical Field
The present invention relates to a reference voltage generating circuit for an integrated circuit and, more particularly, to a reference voltage generating circuit for an integrated circuit for use in an on-chip temperature sensor.
2. Discussion of the Related Art
Generally, a variety of semiconductor devices implemented by integrated circuit chips such as CPUs, memories, gate arrays or the like are used in a variety of electrical products, such as portable personal computers, personal digital assistants (PDAs), servers, portable telephones, or workstations. Many of such electrical products implement a sleep mode to save power, in which most of the circuit components in the products remain in a turn-off state. However, for example, a semiconductor memory, such as a DRAM or the like, belonging to a volatile memory, must perform a self-refreshing operation on data in a memory cell so that the data stored in the memory cell continues to be reserved. The DRAM consumes self-refresh power due to the required self-refreshing operation. It is very important to reduce power consumption in a battery-operated system that requires lower power, which is a critical issue.
One attempt to reduce power consumption required for the self-refresh is to change a refresh period depending on temperature. A time period for which data is reserved in the DRAM becomes longer as temperature becomes lower. Accordingly, it is certain that dividing a temperature area into several temperature areas and lowering the frequency of a refresh clock relatively in lower temperature areas of the temperature areas reduces power consumption. Here, in order to determine internal temperature of the DRAM, a built-in temperature sensor having less power consumption is necessary and in turn a reference voltage generator for providing a reference voltage to the temperature sensor becomes necessary. In such a reference voltage generator, a high-speed response characteristic and stability of operation is a very important matter since ON and OFF operations are being iterated for the purpose of reducing power consumption.
A typical circuit configuration of a band-gap reference type of reference voltage generator is shown in FIG. 1.
Referring to FIG. 1, a reference voltage generator 10 includes a first current mirror section composed of P-type MOS transistors MP1 and MP2, a second current mirror section composed of N-type MOS transistors MN1 and MN2, a first resistor R and a first diode D2 serially connected to each other on a first current path, a second diode D1 connected to a second current path, and a driving switching section IN1 and PD1 for applying a driving power supply voltage to a power supply node of the first current mirror section. Here, the junction diodes D2 and D1 connected to branches A and B, respectively, of the first and second current paths have the same dimension. The P-type MOS transistors MP1 and MP2 have a size ratio of 1:1 and the N-type MOS transistors MN1 and MN2 have a size ratio set to 1:1 as well. Here, the size indicates a channel length L multiplied by a gate width W.
The operation of the reference voltage generator shown in FIG. 1 will be described hereinafter.
The driving power supply voltage VDD is applied to the sources of the P-type MOS transistors MP1 and MP2 of the first current mirror section only if the P-type MOS transistor PD1 making up the drive switching section is in a turn-on state.
If the driving power supply voltage is applied to the first current mirror section, the current mirror operations of the P-type MOS transistors MP1 and MP2 and the N-type MOS transistors MN1 and MN2 allow a current of IO:Ir=1:1 to flow, and voltages appearing at the branches A and B become the same level.
In a turn-on period of a typical junction diode, a current formula becomes I=Is{e(VD/VT)−1}≈Is*e(VD/VT), where Is is a reverse saturation current, VD is a diode voltage, and VT is kT/q and indicates a thermal voltage.
Since the voltages appeared at the branches A and B are identical to each other, VA=VB=VD1=VD2+Ir*R and IO=Is*e(VD1/VT)→VD1=VT*ln(IO/Is).
In addition, since Ir=Is*e(VD2/VT)→VD2=VT*ln(Ir/Is)=VT*ln(M*IO/Is), VT*ln(IO/Is)=VT*ln(M*OI/Is)+Ir*R.
Accordingly, since Ir=VT*ln(M)/R, a current proportional to the temperature will flow through the branch A. On the other hand, a voltage across the branch B appears as VB=VD1=VT*ln(IO/Is).
Normally, since the reverse saturation current Is significantly increases with increase of the temperature relative to the VT, the diode voltage has a feature of decrease with the temperature. That is, since the VB decreases with temperature increase, IO decreases with the temperature.
Consequently, if the driving power supply voltage VDD is applied, a reference voltage OUT having a temperature-compensated, constant voltage level is outputted from the reference voltage output node al of the reference voltage generator.
However, in the circuit as shown in FIG. 1, if a switching control signal EN is alternated between a high state and a low state in a short time period, the P-type MOS transistor PD1 is repeatedly turned ON and OFF. The operation of the reference voltage generator may cause the following problem.
First, if a high switching control signal EN is applied, the P-type MOS transistor PD1 is turned ON and in turn the P-type MOS transistors MP1 and MP2 of the first current mirror section begin to be turned ON. At this time, since the voltage level of the reference voltage output node a1 rises earlier than the voltage level of the node a2 because of properties of the circuit, the P-type MOS transistors MP1 and MP2 may be turned OFF before the voltage level at the node a2 rises to a sufficient level. In this case, since the voltage of the node a2 does not reach a required sufficient level, it causes the current mirror operation of the second current mirror section, which is composed of the N-type MOS transistors MN1 and MN2, to be unstable or even to be disabled.
As such, an early turn-off operation of the P-type MOS transistors MP1 and MP2 in a period for which the driving power supply voltage VDD is initially supplied makes the current mirror operation of the second current mirror section unstable. Accordingly, a time period until the voltage level of the reference voltage output node a1 is set to a normal voltage level is long, resulting in deterioration of high-speed response characteristics of the circuit.
If the switching control signal EN is applied in the low state, the P-type MOS transistor PD1 is turned OFF and in turn the P-type MOS transistors MP1 and MP2 of the first current mirror section and the N-type MOS transistors MN1 and MN2 of the second current mirror section are also turned OFF. In this case, the first resistor R and the first diode D2 may make the voltage level of the node a3 in a floating state. If the node a3 is in the floating state, a long time is taken until the first and second current mirror sections mature into their normal operation when the switching control signal EN is applied back in the high state.
In the conventional circuit as shown in FIG. 1, a setup time for the circuit is long since a long time is taken for stabilizing a voltage level at each node when power is supplied. Therefore, the circuit has a problem in that a high-speed response characteristic is degraded. Further, there is a problem in that if particular nodes become in a floating state upon power-off, more time is initially taken until the voltage level is stabilized upon next power application.
Accordingly, for a reference voltage generating circuit which is used at places where power becomes on/off repeatedly, a technique is required allowing a voltage level at each node to reach a required voltage level as soon as possible after power is supplied. That is, there is a need for a reference voltage generating circuit having a high-speed response characteristic and guaranteeing stability of operation.